The present invention relates, in general, to semiconductor devices, and more particularly to a sense circuit suitable for use in semiconductor devices.
In the past, the semiconductor industry has utilized a variety of circuits and techniques for sensing the state of information stored in memories and other types of semiconductor devices. Typically, such circuits utilized one of two sates to store information within each cell of the memory. For large size memory erase, utilizing memory cells that store only two states results in the memory array occupying a large amount of semiconductor area thereby resulting in high semiconductor costs.
Also, the prior circuits generally utilize voltage sensing amplifiers that sense the voltage value of information in each cell of the memory array. When the memory cell read, it takes along time for the voltage to charge capacitance's coupled to the memory cell thereby requiring a long read cycle for the memory array.
Accordingly, it is desirable to have a sense circuit that consumes a small semiconductor area, that can sense more than two states that are stored within a memory cell, and that results in a fast read cycle for the memory array or memory cells.